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LTC4251/LTC4251-1/ LTC4251-2 Negative Voltage Hot Swap Controllers in SOT-23
FEATURES

DESCRIPTIO
Allows Safe Board Insertion and Removal from a Live -48V Backplane Floating Topology Permits Very High Voltage Operation Programmable Analog Current Limit with Circuit Breaker Timer Fast Response Time Limits Peak Fault Current Programmable Timer Programmable Undervoltage/Overvoltage Protection Low Profile (1mm) ThinSOTTM Package
The LTC(R)4251/LTC4251-1/LTC4251-2 negative voltage Hot SwapTM controllers allow a board to be safely inserted and removed from a live backplane. Output current is controlled by three stages of current limiting: a timed circuit breaker, active current limiting and a fast feedforward path that limits peak current under worst-case catastrophic fault conditions. Programmable undervoltage and overvoltage detectors disconnect the load whenever the input supply exceeds the desired operating range. The supply input is shunt regulated, allowing safe operation with very high supply voltages. A multifunction timer delays initial start-up and controls the circuit breaker's response time. The LTC4251 UV/OV thresholds are designed to match the standard telecom operating range of - 43V to - 75V. The LTC4251-1 UV/OV thresholds extend the operating range to encompass - 36V to - 72V. The LTC4251-2 implements a UV threshold of - 43V only. All parts are available in the 6-Pin SOT-23 package.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. ThinSOT and Hot Swap are trademarks of Linear Technology Corporation.
APPLICATIO S

Hot Board Insertion Electronic Circuit Breaker -48V Distributed Power Systems Negative Power Supply Control Central Office Switching Programmable Current Limiting Circuit High Availability Servers Disk Arrays
TYPICAL APPLICATIO
GND GND (SHORT PIN) R1 402k 1% C1 10nF R2 32.4k 1%
-48V, 2.5A Hot Swap Controller
RIN* 10k 500mW 3 VIN UV/OV 4 GATE CL 100F CIN 1F
+
LOAD VOUT Q1 IRF530S 3
GATE 5V/DIV
5
6
LTC4251 TIMER SENSE VEE CT 150nF 2 1 RC 10 CC 18nF 4 1 RS 0.02 2
425112 TA01
SENSE 2.5A/DIV
VOUT 20V/DIV
-48V *TWO 0.25W RESISTORS IN SERIES FOR RIN ON THE PCB ARE RECOMMENDED.
U
Start-Up Behavior
1ms/DIV
425112 TA02
U
U
425112fa
1
LTC4251/LTC4251-1/ LTC4251-2
ABSOLUTE
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW SENSE 1 VEE 2 VIN 3 6 GATE 5 UV/OV* 4 TIMER
(Note 1), All Voltages are Referred to VEE
Current into VIN (100s Pulse) ........................... 100mA Minimum VIN Voltage ........................................... - 0.3V Gate, UV/OV, Timer Voltage .......................- 0.3V to 16V Sense Voltage ............................................- 0.6V to 16V Current Out of Sense Pin (20s Pulse) ............. -200mA Maximum Junction Temperature .......................... 125C Operating Temperature Range LTC4251C/LTC4251-1C/LTC4251-2C ...... 0C to 70C LTC4251I/LTC4251-1I/LTC4251-2I .... - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
S6 PACKAGE 6-LEAD PLASTIC SOT-23 *UV FOR LTC4251-2
TJMAX = 125C, JA = 256C/W
ORDER PART NUMBER LTC4251CS6 LTC4251IS6 LTC42511CS6 LTC4251-1IS6 LTC42512CS6 LTC4251-2IS6
S6 PART MARKING LTUQ LTUR LTQU LTQV LTK6 LTAAZ
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges.
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Notes 2, 3)
SYMBOL VZ rZ IIN VLKO VLKH VCB VACL VFCL IGATE PARAMETER VIN to VEE Zener Voltage VIN to VEE Zener Dynamic Impedance VIN Supply Current VIN Undervoltage Lockout VIN Undervoltage Lockout Hysteresis Circuit Breaker Current Limit Voltage Analog Current Limit Voltage Fast Current Limit Voltage GATE Pin Output Current VCB = (VSENSE - VEE) VACL = (VSENSE - VEE) VFCL = (VSENSE - VEE) UV/OV = 4V, VSENSE = VEE, VGATE = 0V (Sourcing) UV/OV = 4V, VSENSE - VEE = 0.15V, VGATE = 3V (Sinking) UV/OV = 4V, VSENSE - VEE = 0.3V, VGATE = 1V (Sinking) VGATE - VEE, IIN = 2mA (Before Gate Ramp-Up) LTC4251/LTC4251-2 LTC4251-1 LTC4251/LTC4251-2 LTC4251-1 LTC4251/LTC4251-2 LTC4251-1 LTC4251 LTC4251-1

ELECTRICAL CHARACTERISTICS
CONDITIONS IIN = 2mA IIN = 2mA to 30mA UV/OV = 4V, VIN = (VZ - 0.3V) Coming out of UVLO (Rising VIN)

MIN 11.5
TYP 13 5 0.8 9.2 1
MAX 14.5 2 11.5 60 120 300 80
UNITS V mA V V mV mV mV A mA mA V V V V V V V V
40 80 150 40
50 100 200 58 17 190 12 0.5 3.225 2.420 2.925 2.160 0.30 0.26
VGATE VGATEL VUVHI VUVLO VUVHST VOVHI
External MOSFET Gate Drive Gate Low Threshold UV Threshold High UV Threshold Low UV Hysteresis OV Threshold High
10 3.075 2.300 2.775 2.050
VZ 3.375 2.540 3.075 2.270
5.85 5.86
6.15 6.17
6.45 6.48
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2
U
V V
W
U
U
WW
W
LTC4251/LTC4251-1/ LTC4251-2
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Notes 2, 3)
SYMBOL VOVLO VOVHST ISENSE IINP VTMRH VTMRL ITMR PARAMETER OV Threshold Low OV Hysteresis SENSE Input Current UV/OV Input Current Timer Voltage High Threshold Timer Voltage Low Threshold Timer Current Timer On (Initial Cycle, Sourcing), VTMR = 2V Timer Off (Initial Cycle, Sinking), VTMR = 2V Timer On (Circuit Breaker, Sourcing), VTMR = 2V Timer Off (Cooling Cycle, Sinking), VTMR = 2V LTC4251/LTC4251-1 CONDITIONS LTC4251 LTC4251-1 LTC4251 LTC4251-1 UV/OV = 4V, VSENSE = 50mV UV/OV = 4V

ELECTRICAL CHARACTERISTICS
MIN 5.25 5.61
TYP 5.55 5.91 0.60 0.26
MAX 5.85 6.21
UNITS V V V V A
-30
-15 0.1 4 1 5.8 28 230 5.8 0.7 1 1
A V V A mA A A s s
tPLLUG tPHLOG
UV Low to GATE Low OV High to GATE Low
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to VEE unless otherwise specified. Note 3: UV/OV = 4V refers to UV = 4V for the LTC4251-2.
TYPICAL PERFOR A CE CHARACTERISTICS
2000 1800 1600 1400
IIN (A)
IIN vs Temperature
VIN = (VZ - 0.3V)
1000
IIN (mA)
1200 1000 800 600 400 200 0 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
425112 G01
rZ ()
UW
UV/OV = 4V refers to UV = 4V for the LTC4251-2. rZ vs Temperature
IIN = 2mA
IIN vs VIN
TA = -40C 100 TA = 25C 10
10 9 8 7 6 5
TA = 85C TA = 125C
1
4 3
0.1
0
2
4
6
8 10 12 14 16 18 20 22 VIN (V)
425112 G02
2 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
425112 G03
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3
LTC4251/LTC4251-1/ LTC4251-2 TYPICAL PERFOR A CE CHARACTERISTICS
VZ vs Temperature
14.5 IIN = 2mA
14.0
VLKO (V)
13.5 VZ (V)
10.0 9.5 9.0
VLKH
13.0
12.5
12.0 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
425112 G04
Circuit Breaker Current Limit Voltage VCB vs Temperature
60 58 56 54
120 115 110
50 48 46 44 42 40 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
425112 G07
100 95 90 85 80 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
425112 G08
VFCL (mV)
VCB (mV)
VACL (V)
52
IGATE (Source) vs Temperature
70 UV/0V = 4V TIMER = 0V 65 VSENSE = VEE VGATE = 0V 60
IGATE (mA) IGATE (A)
30 25 20
IGATE (mA)
55 50 45 40 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
425112 G10
4
UW
UV/OV = 4V refers to UV = 4V for the LTC4251-2. Undervoltage Lockout Hysteresis VLKH vs Temperature
Undervoltage Lockout VLKO vs Temperature
12.0 11.5 11.0 10.5 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 5 25 45 65 85 105 125 TEMPERATURE (C)
425112 G05
8.5 8.0 -55 -35 -15
0 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
425112 G06
Analog Current Limit Voltage VACL vs Temperature
300 275 250 225 200 175
Fast Current Limit Voltage VFCL vs Temperature
105
150 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
425112 G09
IGATE (ACL, Sink) vs Temperature
400 UV/0V = 4V TIMER = 0V VSENSE - VEE = 0.15V VGATE = 3V 350 300 250 200 150 100 5 0 -55 -35 -15 50 5 25 45 65 85 105 125 TEMPERATURE (C)
425112 G11
IGATE (FCL, Sink) vs Temperature
UV/0V = 4V TIMER = 0V VSENSE - VEE = 0.3V VGATE = 1V
15 10
0 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
425112 G12
425112fa
LTC4251/LTC4251-1/ LTC4251-2 TYPICAL PERFOR A CE CHARACTERISTICS
VGATE vs Temperature
14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 10.5 10.0 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
425112 G13
UV/0V = 4V VTMR = 0V VSENSE = VEE
UV THRESHOLD (V)
VGATEL (V)
VGATE (V)
UV Threshold vs Temperature
2.55 2.50 2.45 LTC4251-1 6.25 VUVHI 6.45
UV THRESHOLD (V)
OV THRESHOLD (V)
OV THRESHOLD (V)
2.40 2.35 2.30 2.25 2.20 2.15 2.10 2.05 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
425112 G16
ISENSE vs Temperature
-10 -12 -14 -16 -ISENSE (mA) 0.1 0.01
TIMER THRESHOLD (V)
ISENSE (A)
-18 -20 -22 -24 -26 -28 -30 -55 -35 -15 UV/0V = 4V TIMER = 0V GATE = HIGH VSENSE - VEE = 50mV 5 25 45 65 85 105 125 TEMPERATURE (C)
425112 G19
UW
VUVLO
UV/OV = 4V refers to UV = 4V for the LTC4251-2. UV Threshold vs Temperature
3.375 LTC4251/LTC4251-2 3.275 3.175 3.075 2.975 2.875 2.775 -55 -35 -15 VUVH
VGATEL vs Temperature
0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
425112 G14
UV/0V = 4V, VTMR = 0V, GATE THRESHOLD BEFORE RAMP-UP
VUVL
5 25 45 65 85 105 125 TEMPERATURE (C)
425112 G15
OV Threshold vs Temperature
6.51
LTC4251 VOVH
OV Threshold vs Temperature
6.41 6.31 6.21 6.11 6.01 5.91 5.81 5.71 VOVLO VOVHI LTC4251-1
6.05 5.85 5.65 5.45 5.25 -55 -35 -15
VOVL
5 25 45 65 85 105 125 TEMPERATURE (C)
425112 G17
5.61 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
425112 G18
ISENSE vs (VSENSE - VEE)
5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5
TIMER Threshold vs Temperature
VTMRH
1.0
10 UV/0V = 4V TIMER = 0V GATE = HIGH TA = 25C 1.5 2.0
100
VTMRL
1000 -1.5 -1.0 -0.5 0 0.5 1.0 (VSENSE - VEE) (V)
0 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
425112 G21
425112 G20
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5
LTC4251/LTC4251-1/ LTC4251-2 TYPICAL PERFOR A CE CHARACTERISTICS
ITMR (Initial Cycle, Sourcing) vs Temperature
10 9 8 7 ITMR (mA) ITMR (A) 6 5 4 3 2 1 0 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
425112 G22
30 25 20 15 10 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
425112 G23
ITMR (A)
ITMR (Cooling Cycle, Sinking) vs Temperature
10 9 8 7 1.3 1.2 1.1
ITMR (A)
6 5 4 3 2 1 0 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
425112 G25
DELAY (s)
6
UW
UV/OV = 4V refers to UV = 4V for the LTC4251-2. ITMR (Circuit Breaking, Sourcing) vs Temperature
280
ITMR (Initial Cycle, Sinking) vs Temperature
50 45
260
40 35
240
220
200
180 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
425112 G24
t PLLUG and t PHLOG vs Temperature
tPHLOG (LTC4251/LTC4251-1) 1.0 0.9 0.8 tPLLUG 0.7 0.6 0.5 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
425112 G26
425112fa
LTC4251/LTC4251-1/ LTC4251-2
PI FU CTIO S
UV/OV refers to the UV pin for the LTC4251-2. The OV comparator in the LTC4251-2 is disabled. All references in the text to overvoltage, OV, VOVHI and VOVLO do not apply to the LTC4251-2.
SENSE (Pin 1): Circuit Breaker/Current Limit SENSE Pin. Load current is monitored by sense resistor RS connected between SENSE and VEE, and controlled in three steps. If SENSE exceeds VCB (50mV), the circuit breaker comparator activates a 230A TIMER pin pull-up current. The LTC4251/LTC4251-1/LTC4251-2 latch off when CT charges to 4V. If SENSE exceeds VACL (100mV), the analog current limit amplifier pulls GATE down and regulates the MOSFET current at VACL/RS. In the event of a catastrophic shortcircuit, SENSE may overshoot 100mV. If SENSE reaches VFCL (200mV), the fast current limit comparator pulls GATE low with a strong pull-down. To disable the circuit breaker and current limit functions, connect SENSE to VEE. Kelvin-sense connections between the sense resistor and the VEE and SENSE pins are strongly recommended, see Figure 6. VEE (Pin 2): Negative Supply Voltage Input. Connect this pin to the negative side of the power supply. VIN (Pin 3): Positive Supply Input. Connect this pin to the positive side of the supply through a dropping resistor. A shunt regulator typically clamps VIN at 13V. An internal undervoltage lockout (UVLO) circuit holds GATE low until the VIN pin is greater than VLKO (9.2V), overriding UV/OV. If UV is high, OV is low and VIN comes out of UVLO, TIMER starts an initial timing cycle before initiating a GATE ramp up. If VIN drops below approximately 8.2V, GATE pulls low immediately. TIMER (Pin 4): Timer Input. TIMER is used to generate a delay at start up, and to delay shutdown in the event of an output overload. TIMER starts an initial timing cycle when the following conditions are met: UV is high, OV is low, VIN clears UVLO, TIMER pin is low, GATE is lower than VGATEL and VSENSE - VEE < VCB. A pull-up current of 5.8A then charges CT, generating a time delay. If CT charges to VTMRH (4V) the timing cycle terminates, TIMER quickly pulls low and GATE is activated.
U
U
U
If SENSE exceeds 50mV while GATE is high, a 230A pullup current charges CT. If SENSE drops below 50mV before TIMER reaches 4V, a 5.8A pull-down current slowly discharges CT. In the event that CT eventually integrates up to the 4V VTMRH threshold, TIMER latches high with a 5.8A pull-up source and GATE quickly pulls low. The LTC4251/LTC4251-1/LTC4251-2 fault latches may be cleared by either pulling TIMER low with an external device, or by pulling UV/OV below VUVLO. UV/OV (Pin 5): Undervoltage/Overvoltage Input. This dual function pin detects undervoltage as well as overvoltage. The high threshold at the UV comparator is set at VUVHI with VUVHST hysteresis. The high threshold at the OV comparator is set at VOVHI with VOVHST hysteresis. If UV/OV < VUVLO or UV/OV > VOVHI, GATE pulls low. If UV/OV > VUVHI and UV/OV < VOVLO, the LTC4251/ LTC4251-1/LTC4251-2 attempt to start-up. The internal UVLO at VIN always overrides UV/OV. A low at UV resets an internal fault latch. A high at OV pulls GATE low but does not reset the fault latch. A 1nF to 10nF capacitor at UV/OV eliminates transients and switching noise from affecting the UV/OV thresholds and prevents glitches at the GATE pin. GATE (Pin 6): N-Channel MOSFET Gate Drive Output. This pin is pulled high by a 58A current source. GATE is pulled low by invalid conditions at VIN (UVLO), UV/OV, or the fault latch. GATE is actively servoed to control fault current as measured at SENSE. A compensation capacitor at GATE stabilizes this loop. A comparator monitors GATE to ensure that it is low before allowing an initial timing cycle, GATE ramp up after an overvoltage event, or restart after a current limit fault.
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7
LTC4251/LTC4251-1/ LTC4251-2
BLOCK DIAGRA
VIN 3 VOVHI
VEE UV/OV* 5
-
UV VUVLO VIN 230A 5.8A VIN 4V
VEE
+
LOGIC
-
VIN FCL 22A
TIMER
4
-
VEE 5.8A VEE 1V
+
5k VOS = 10mV ACL
+
VEE
-+ +
-
VEE 1 SENSE
CB
50mV
+-
VEE
425112 BD
2 *UV FOR THE LTC4251-2 ** THE OV COMPARATOR IS DISABLED FOR LTC4251-2 VEE
OPERATIO
Note that for simplicity, the following assumptions are made in the text. Firstly, UV/OV also means the UV pin of the LTC4251-2. Secondly, all overvoltage conditions and references to OV, VOVHI and VOVLO do not apply to the LTC4251-2 as the OV comparator in this part is disabled.
Hot Circuit Insertion When circuit boards are inserted into a live backplane, the supply bypass capacitors can draw huge transient currents from the power bus as they charge. The flow of current damages the connector pins and glitches the power bus, causing other boards in the system to reset. The LTC4251/ LTC4251-1/LTC4251-2 are designed to turn on a circuit board supply in a controlled manner, allowing insertion or removal without glitches or connector damage. Initial Start-Up The LTC4251/LTC4251-1/LTC4251-2 reside on a removable circuit board and control the path between the connector and load or power conversion circuitry with an
external MOSFET switch (see Figure 1). Both inrush control and short-circuit protection are provided by the MOSFET. A detailed schematic is shown in Figure 2. -48V and -48RTN receive power through the longest connector pins, and are the first to connect when the board is inserted. The GATE pin holds the MOSFET off during this time. UV/OV determines whether or not the MOSFET should be turned on based upon internal, high-accuracy thresholds and an external divider. UV/OV does double duty by also monitoring whether or not the connector is seated. The top of the divider detects -48RTN by way of a short connector pin that is the last to mate during the insertion sequence.
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8
-
+
-
+
+
-
W
-
OV** VIN 58A 6 GATE
+
0.5V
200mV
+-
VEE
U
LTC4251/LTC4251-1/ LTC4251-2
OPERATIO
-48RTN LTC4251
PLUG-IN BOARD
-48V BACKPLANE
Figure 1. Basic LTC4251 Hot Swap Topology
LONG -48RTN RIN 10k 500mW SHORT R1 402k 1% C1 10nF CIN 1F UV/OV LTC4251 TIMER VEE SENSE GATE VIN
R2 32.4k 1% LONG -48V
Figure 2. -48V, 2.5A Hot Swap Controller
Interlock Conditions A start-up sequence commences once five initial "interlock" conditions are met: 1. The input voltage VIN exceeds 9.2V (VLKO) 2. The voltage at UV/OV falls within the range of VUVHI to VOVLO (UV > VUVHI, LTC4251-2) 3. The (SENSE - VEE) voltage is <50mV (VCB) 4. The voltage on the timer capacitor (CT) is less than 1V (VTMRL) 5. GATE is less than 0.5V (VGATEL) The first two conditions are continuously monitored and the latter three are checked prior to initial timing or GATE ramp-up. Upon exiting an OV condition, the TIMER pin voltage requirement is inhibited. Details are described in the Applications Information, Timing Waveforms section. TIMER begins the start-up sequence by sourcing 5.8A into CT. If VIN or UV/OV falls out of range, the start-up cycle stops and TIMER discharges CT to less than 1V, then waits until the aforementioned conditions are once again met. If CT successfully charges to 4V, TIMER pulls low and GATE
U
+ +
CLOAD
+
LOW VOLTAGE CIRCUITRY
ISOLATED DC/DC CONVERTER MODULE
is released. GATE sources 58A (IGATE), charging the MOSFET gate and associated capacitance. Two modes of operation are possible during the time the MOSFET is first turning on, depending on the values of external components, MOSFET characteristics and nominal design current. One possibility is that the MOSFET will turn on gradually so that the inrush into the load capacitance remains a low value. The output will simply ramp to -48V and the MOSFET will be fully enhanced. A second possibility is that the load current exceeds the current limit threshold of 100mV/RS. In this case, the LTC4251/ LTC4251-1/LTC4251-2 will ramp the output by sourcing 100mV/RS current into the load capacitance. It is important to set the timer delay so that, regardless of which start-up mode is used, the start-up time is less than the TIMER delay time. If this condition is not met, the LTC4251/ LTC4251-1/LTC4251-2 may shut down after one TIMER delay. Board Removal If the board is withdrawn from the card cage, the UV/OV divider is the first to lose connection. This shuts off the MOSFET and commutates the flow of current in the connector. When the power pins subsequently separate, there is no arcing. Current Control Three levels of protection handle short-circuit and overload conditions. Load current is monitored by SENSE and resistor RS. There are three distinct thresholds at SENSE: 50mV for a timed circuit breaker function; 100mV for an analog current limit loop; and 200mV for a fast, feedforward comparator which limits peak current in the event of a catastrophic short-circuit. If, owing to an output overload, the voltage drop across RS exceeds 50mV, TIMER sources 230A into CT. CT eventually charges to a 4V threshold and the LTC4251/LTC4251-1/ LTC4251-2 latch off. If the overload goes away and SENSE measures less than 50mV, CT slowly discharges (5.8A). In this way the circuit breaker function will also respond to low duty cycle overloads, and accounts for fast heating and slow cooling characteristic of the MOSFET.
425112fa
-
-
425112 F01
+
CL 100F TYP
CT 150nF 3
CC 18nF 4 1 RS 2 20m
RC 10
Q1 IRF530S
425112 F02
9
LTC4251/LTC4251-1/ LTC4251-2
OPERATIO
Higher overloads are handled by an analog current limit loop. If the drop across RS reaches 100mV, the current limiting loop servos the MOSFET gate and maintains a constant output current of 100mV/RS. Note that because SENSE > 50mV, TIMER charges CT during this time and the LTC4251/LTC4251-1/LTC4251-2 will eventually shut down. Low impedance failures on the load side of the LTC4251/ LTC4251-1/LTC4251-2 coupled with 48V or more driving potential can produce current slew rates well in excess of 50A/s. Under these conditions, overshoot is inevitable. A fast SENSE comparator with a threshold of 200mV detects overshoot and pulls GATE low much harder and hence much faster than can the weaker current limit loop. The 100mV/RS current limit loop then takes over, and servos the current as previously described. As before, TIMER runs and latches the LTC4251/LTC4251-1/LTC4251-2 off when CT reaches 4V.
APPLICATIO S I FOR ATIO
SHUNT REGULATOR
A fast responding regulator shunts the LTC4251/ LTC4251-1/LTC4251-2 VIN pin. Power is derived from -48RTN by an external current limiting resistor. The shunt regulator clamps VIN to 13V (VZ). A 1F decoupling capacitor at VIN filters supply transients and contributes a short delay at start-up. A 10k 1/2W (RIN) resistor can be two 5k 1/4W resistors in series. INTERNAL UNDERVOLTAGE LOCKOUT (UVLO) Internal circuitry monitors VIN for undervoltage. The exact thresholds are defined by VLKO and its hysteresis, VLKH. When VIN rises above 9.2V (VLKO) the chip is enabled; below 8.2V (VLKO-VLKH) it is disabled and GATE is pulled low. The UVLO function at VIN should not be confused with the UV/OV pin. These are completely separate functions.
10
U
W
UU
U
The LTC4251/LTC4251-1/LTC4251-2 circuit breaker latch is reset by either pulling UV/OV momentarily low, or dropping the input voltage VIN below the internal UVLO threshold of 8.2V. Although short-circuits are the most obvious fault type, several operating conditions may invoke overcurrent protection. Noise spikes from the backplane or load, input steps caused by the connection of a second, higher voltage supply, transient currents caused by faults on adjacent circuit boards sharing the same power bus, or the insertion of non-hot swappable products could cause higher than anticipated input current and temporary detection of an overcurrent condition. The action of TIMER and CT rejects these events allowing the LTC4251/ LTC4251-1/LTC4251-2 to "ride out" temporary overloads and disturbances that would trip a simple current comparator and in some cases, blow a fuse.
(Refer to Block Diagram)
UV/OV COMPARATORS Two hysteretic comparators for detecting under- and overvoltage conditions, with the following thresholds, monitor the dual function UV/OV pin: UV turning on at VUVHI UV turning off at VUVLO OV turning off at VOVHI OV turning on at VOVLO The UV and OV trip point ratio for LTC4251 is designed to match the standard telecom operating range of 43V to 75V. The LTC4251-2 implements a UV threshold of 43V only. A divider (R1, R2) is used to scale the supply voltage. Using R1 = 402k and R2 = 32.4k gives a typical operating range of 43.2V to 74.4V. The under- and overvoltage shutdown thresholds are then 39.2V and 82.5V. 1% divider resistors are recommended to preserve threshold accuracy. The same resistor values can be used for the LTC4251-2.
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LTC4251/LTC4251-1/ LTC4251-2
APPLICATIO S I FOR ATIO
The R1-R2 divider values shown in the Typical Application set a standing current of slightly more than 100A, and define an impedance at UV/OV of 30k. In most applications, 30k impedance coupled with 300mV UV hysteresis makes the LTC4251/LTC4251-1/LTC4251-2 insensitive to noise. If more noise immunity is desired, add a 1nF to 10nF filter capacitor from UV/OV to VEE. The UV and OV trip point thresholds for the LTC4251-1 are designed to encompass the standard telecom operating range of -36V to -72V. A divider (R1, R2) is used to scale the supply voltage. Using R1 = 442k and R2 = 34.8k gives a typical operating range of 33.2V to 81V. The typical under- and overvoltage shutdown thresholds are then 29.6V and 84.5V. 1% divider resistors are recommended to preserve threshold accuracy. The R1-R2 divider values shown in the Typical Application set a standing current of slightly more than 100A, and define an impedance at UV/OV of 32k. In most applications, 32k impedance coupled with 260mV UV hysteresis makes the LTC4251-1 insensitive to noise. If more noise immunity is desired, add a 1nF to 10nF filter capacitor from UV/OV to VEE. UV/OV OPERATION A low input to the UV comparator will reset the chip and pull the GATE and TIMER pins low. A low-to-high UV transition will initiate an initial timing sequence if the three remaining interlock conditions are met. Overvoltage conditions detected by the OV comparator will also pull GATE low, thereby shutting down the load, but it will not reset the circuit breaker latch. Returning the supply voltage to an acceptable range restarts the GATE pin provided all interlock conditions except TIMER are met. TIMER The operation of the TIMER pin is somewhat complex as it handles several key functions. A capacitor, CT, is used at TIMER to provide timing for the LTC4251/LTC4251-1/ LTC4251-2. Four different charging and discharging modes are available at TIMER:
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1. 5.8A slow charge; initial timing delay 2. 230A fast charge; circuit breaker delay 3. 5.8A slow discharge; circuit breaker "cool-off" 4. Low impedance switch; resets capacitor after initial timing delay, in undervoltage lockout, and in overvoltage For initial startup, the 5.8A pull-up is used. The low impedance switch is turned off and the 5.8A current source is enabled when the four interlock conditions are met. CT charges to 4V in a time period given by:
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t=
4V * C T 5.8A
(1)
When CT reaches 4V (VTMRH), the low impedance switch turns on and discharges CT. The GATE output is enabled and the load turns on. CIRCUIT BREAKER TIMER OPERATION If the SENSE pin detects more than 50mV across RS, the TIMER pin charges CT with 230A. If CT charges to 4V, the GATE pin pulls low and the LTC4251/LTC4251-1/ LTC4251-2 latch off. The part remains latched off until either the UV/OV pin is momentarily pulsed low, or VIN dips into UVLO and is then restored. The circuit breaker timeout period is given by
t= 4V * C T 230A
(2)
Intermittent overloads may exceed the 50mV threshold at SENSE, but if their duration is sufficiently short TIMER will not reach 4V and the LTC4251/LTC4251-1/LTC4251-2 will not latch off. To handle this situation, the TIMER discharges CT slowly with a 5.8A pull-down whenever the SENSE voltage is less than 50mV. Therefore any intermittent overload with an aggregate duty cycle of 2.5% or more will eventually trip the circuit breaker and latch off the LTC4251/LTC4251-1/LTC4251-2. Figure 3 shows the circuit breaker response time in seconds normalized to 1F. The asymmetric charging and discharging of CT is a fair gauge of MOSFET heating.
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11
LTC4251/LTC4251-1/ LTC4251-2
APPLICATIO S I FOR ATIO
10
NORMALIZED RESPONSE TIME (s/F)
1
0.1
4 t = CT(F) (235.8 * D) - 5.8
0.01
0
20 40 60 80 FAULT DUTY CYCLE, D (%)
100
425112 F03
Figure 3. Circuit Breaker Response Time
GATE GATE is pulled low to VEE under any of the following conditions: in UVLO, during the initial timing cycle, in an overvoltage condition, or when the LTC4251/LTC4251-1/ LTC4251-2 are latched off after a short-circuit. When GATE turns on, a 58A current source charges the MOSFET gate and any associated external capacitance. VIN limits gate drive to no more than 14.5V. Gate-drain capacitance (CGD) feed through at the first abrupt application of power can cause a gate-source voltage sufficient to turn on the MOSFET. A unique circuit pulls GATE low with practically no usable voltage at VIN, and eliminates current spikes at insertion. A large external gate-source capacitor is thus unnecessary for the purpose of compensating CGD. Instead, a smaller value (10nF) capacitor CC is adequate. CC also provides compensation for the analog current limit loop. SENSE The SENSE pin is monitored by the circuit breaker (CB) comparator, the analog current limit (ACL) amplifier, and the fast current limit (FCL) comparator. Each of these three measures the potential of SENSE relative to VEE. If SENSE exceeds 50mV, the CB comparator activates the 230A TIMER pull-up. At 100mV, the ACL amplifier servos the MOSFET current, and at 200mV the FCL comparator abruptly pulls GATE low in an attempt to bring the MOSFET current under control. If any of these conditions persists long enough for TIMER to charge CT to 4V (see Equation (2)), the LTC4251/LTC4251-1/LTC4251-2 latch off and pull GATE low.
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If the SENSE pin encounters a voltage greater than 100mV, the ACL amplifier will servo GATE downwards in an attempt to control the MOSFET current. Since GATE overdrives the MOSFET in normal operation, the ACL amplifier needs time to discharge GATE to the threshold of the MOSFET. For a mild overload, the ACL amplifier can control the MOSFET current, but in the event of a severe overload the current may overshoot. At SENSE = 200mV, the FCL comparator takes over, quickly discharging the GATE pin to near VEE potential. FCL then releases, and the ACL amplifier takes over. All the while TIMER is running. The effect of FCL is to add a nonlinear response to the control loop in favor of reducing MOSFET current. Owing to inductive effects in the system, FCL typically overcorrects the current limit loop, and GATE undershoots. A zero in the loop (resistor RC in series with the gate capacitor) helps the ACL amplifier recover. SHORT-CIRCUIT OPERATION Circuit behavior arising from a load-side low impedance short is shown in Figure 4. Initially, the current overshoots the analog current limit level of VSENSE = 100mV (Trace 2) as the GATE pin works to bring VGS under control (Trace 3). The overshoot glitches the backplane in the negative direction, and when the current is reduced to 100mV/RS the backplane responds by glitching in the positive direction. TIMER commences charging CT (Trace 4) while the analog current limit loop maintains the fault current at 100mV/RS, which in this case is 5A (Trace 2). Note that the backplane voltage (Trace 1) sags under load. When CT reaches 4V, GATE turns off, the load current drops to zero and the backplane rings up to over 100V. The positive peak is usually limited by avalanche breakdown in the MOSFET, and can be further limited by adding a zener diode across the input from - 48V to - 48RTN, such as Diodes Inc. SMAT70A. A low-impedance short on one card may influence the behavior of others sharing the same backplane. The initial glitch and backplane sag as seen in Figure 4, Trace 1, can rob charge from output capacitors on adjacent cards. When the faulty card shuts down, current flows in to refresh the
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LTC4251/LTC4251-1/ LTC4251-2
APPLICATIO S I FOR ATIO
capacitors. If LTC4251, LTC4251-1 or LTC4251-2s are used throughout, they respond by limiting the inrush current to a value of 100mV/RS. If CT is sized correctly, the capacitors will recharge long before CT times out.
SUPPLY RING OWING TO CURRENT OVERSHOOT ONSET OF OUTPUT SHORT-CIRCUIT SUPPLY RING OWING TO MOSFET TURN-OFF
-48RTN 50V/DIV
TRACE 1
SENSE 200mV/DIV GATE 10V/DIV
FAST CURRENT LIMIT ANALOG CURRENT LIMIT
TRACE 2
TRACE 3 TRACE 4
LATCH OFF
TIMER
5V/DIV
CTIMER RAMP
2ms/DIV
425112 F04
Figure 4. Output Short-Circuit Behavior (All Waveforms are Referenced to VEE)
MOSFET SELECTION The external MOSFET switch must have adequate safe operating area (SOA) to charge the load capacitance on start-up and handle short-circuit conditions until TIMER latchoff. These considerations take precedence over DC current ratings. A MOSFET with adequate SOA for a given application can always handle the required current, but the opposite cannot be said. Consult the manufacturer's MOSFET data sheet for safe operating area and effective transient thermal impedance curves. MOSFET selection is a three-step process. First, RS is calculated, and then the time required to charge the load capacitance is determined. This timing, along with the maximum short-circuit current and maximum input voltage defines an operating point that is checked against the MOSFET's SOA curve. To begin a design, first specify the required load current and load capacitance, IL and CL. The circuit breaker current trip point (50mV/RS) should be set to accommodate the maximum load current. Note that maximum input current to a DC/DC converter is expected at VSUPPLY (MIN). RS is given by:
RS =
40mV IL(MAX)
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where 40mV represents the guaranteed minimum circuit breaker threshold. During the initial charging process, the LTC4251/ LTC4251-1/LTC4251-2 may operate the MOSFET in current limit, forcing 80mV to 120mV across RS. The minimum inrush current is given by:
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IINRUSH(MIN)=
80mV RS
(4)
Maximum short-circuit current limit is calculated using maximum VSENSE, or:
ISHORT - CIRCUIT(MAX) = 120mV RS
(5)
The TIMER capacitor CT must be selected based on the slowest expected charging rate; otherwise TIMER might time out before the load capacitor is fully charged. A value for CT is calculated based on the maximum time it takes the load capacitor to charge. That time is given by:
t CL CHARGE = C * V C L * VSUPPLY(MAX) = I IINRUSH(MIN)
(6)
Substituting Equation (4) for IINRUSH(MIN) and equating (6) with (2) gives:
CT =
C L * VSUPPLY(MAX) * RS * 230A (4V * 80mV)
(7)
Returning to Equation (2), the TIMER period is calculated and used in conjunction with V SUPPLY(MAX) and ISHORT-CIRCUIT(MAX) to check the SOA curves of a prospective MOSFET. As a numerical design example, consider a 30W load, which requires 1A input current at 36V. If VSUPPLY(MAX) = 72V and CL = 100F, Equation (3) gives RSENSE = 40m; Equation (7) gives CT = 207nF. To account for errors in RSENSE, CT, TIMER current (230A) and TIMER threshold (4V), the calculated value should be multiplied by 1.5, giving a nearest standard value of CT = 330nF. If a short-circuit occurs, a current of up to 120mV/40m = 3A will flow in the MOSFET for 5.7ms as dictated by
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(3)
13
LTC4251/LTC4251-1/ LTC4251-2
APPLICATIO S I FOR ATIO
CT = 330nF in Equation (2). The MOSFET must be selected based on this criterion. The IRF530S can handle 100V and 3A for 10ms, and is safe to use in this application. SUMMARY OF DESIGN FLOW To summarize the design flow, consider the application shown in Figure 2, which was designed for 50W: Calculate maximum load current: 50W/36V = 1.4A; allowing 83% converter efficiency, IIN (MAX) = 1.7A. Calculate RS: from Equation (3) RS = 20m. Calculate CT: from Equation (7) CT = 150nF (including 1.5X correction factor). Calculate TIMER period: from Equation (2) the shortcircuit time-out period is t = 2.6ms. Calculate maximum short-circuit current: from Equation (5) maximum short-circuit current could be as high as 120mV/20m = 6A. Consult MOSFET SOA curves: the IRF530S can handle 6A at 72V for 5ms, so it is safe to use in this application. FREQUENCY COMPENSATION The LTC4251/LTC4251-1/LTC4251-2 typical frequency compensation network for the analog current limit loop is a series RC (10) and CC connected to VEE. Figure 5 depicts the relationship between the compensation capacitor CC and the MOSFET's CISS. The line in Figure 5 is used to select a starting value for CC based upon the MOSFET's CISS specification. Optimized values for CC are shown for several popular MOSFETs. Differences in the optimized value of CC versus the starting value are small. Nevertheless, compensation values should be verified by board level short-circuit testing. As seen in Figure 4 previously, at the onset of a shortcircuit event, the input supply voltage can ring dramatically owing to series inductance. If this voltage avalanches the MOSFET, current continues to flow through the MOSFET to the output. The analog current limit loop cannot control this current flow and therefore the loop undershoots. This effect cannot be eliminated by frequency compensation. A
COMPENSATION CAPACITOR CC (nF)
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zener diode is required to clamp the input supply voltage and prevent MOSFET avalanche.
60 50 40 30 20 10 0 IRF540 IRF530 IRF740 MTY100N10E IRF3710 0 2000 6000 4000 MOSFET CISS (pF) 8000
425112 F05
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Figure 5. Recommended Compensation Capacitor CC vs MOSFET CISS
SENSE RESISTOR CONSIDERATIONS For proper circuit breaker operation, Kelvin-sense PCB connections between the sense resistor and the VEE and SENSE pins are strongly recommended. The drawing in Figure 6 illustrates the correct way of making connections between the LTC4251/LTC4251-1/LTC4251-2 and the sense resistor. PCB layout should be balanced and symmetrical to minimize wiring errors. In addition, the PCB layout for the sense resistor should include good thermal management techniques for optimal sense resistor power dissipation.
CURRENT FLOW FROM LOAD CURRENT FLOW TO -48V BACKPLANE
SENSE RESISTOR TRACK WIDTH W: 0.03" PER AMP ON 1 OZ COPPER W
425112 F06
TO SENSE
TO VEE
Figure 6. Making PCB Connections to the Sense Resistor
TIMING WAVEFORMS System Power-Up Figure 7 details the timing waveforms for a typical powerup sequence in the case where a board is already installed in the backplane and system power is applied abruptly. At time point 1, the supply ramps up, together with UV/OV
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LTC4251/LTC4251-1/ LTC4251-2
APPLICATIO S I FOR ATIO
and VOUT. VIN follows at a slower rate as set by the VIN bypass capacitor. At time point 2, VIN exceeds VLKO and the internal logic checks for VUVHI < UV/OV < VOVLO, TIMER < VTMRL, GATE < VGATEL and SENSE < VCB. When all conditions are met, an initial timing cycle starts and the TIMER capacitor is charged by a 5.8A current source pull-up. At time point 3, TIMER reaches the VTMRH threshold and the initial timing cycle terminates. The TIMER capacitor is then quickly discharged. At time point 4, the VTMRL threshold is reached and the conditions of GATE < VGATEL and SENSE < VCB must be satisfied before a startup cycle is allowed to begin. GATE sources 58A into the external MOSFET gate and compensation network. When the GATE voltage reaches the MOSFET's threshold, current begins flowing into the load capacitor. At time point 5, the SENSE voltage (VSENSE - VEE ) reaches the VCB threshold and activates the TIMER. The TIMER capacitor is charged by a 230A current-source pull-up. At time point 6, the analog current limit loop activates. Between time point 6 and time point 7, the GATE voltage is held essentially constant and the sense voltage is regulated at VACL. As the load capacitor nears full charge, its current begins to decline. At point 7, the load current falls and the sense voltage drops below VACL. The analog current limit loop shuts off and the GATE pin ramps further. At time point 8, the sense voltage drops below VCB and TIMER now discharges through a 5.8A current source pulldown. At time point 9, GATE reaches its maximum voltage as determined by VIN. Live Insertion with Short Pin Control of UV/OV In this example as shown in Figure 8, power is delivered through long connector pins whereas the UV/OV divider makes contact through a short pin. This ensures the power connections are firmly established before the LTC4251/ LTC4251-1/LTC4251-2 are activated. At time point 1, the power pins make contact and VIN ramps through VLKO. At time point 2, the UV/OV divider makes contact and its voltage exceeds VUVHI. In addition, the internal logic checks for VUVHI < UV/OV < VOVHI, TIMER < VTMRL, GATE < VGATEL and SENSE < VCB. When all conditions are met, an initial timing cycle starts and the TIMER capacitor is charged by a 5.8A current source pull-up. At time point 3, TIMER reaches the VTMRH threshold and the initial
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timing cycle terminates. The TIMER capacitor is then quickly discharged. At time point 4, the VTMRL threshold is reached and the conditions of GATE < VGATEL and SENSE < VCB must be satisfied before a start-up cycle is allowed to begin. GATE sources 58A into the external MOSFET gate and compensation network. When the GATE voltage reaches the MOSFET's threshold, current begins flowing into the load capacitor. At time point 5, the SENSE voltage (VSENSE - VEE ) reaches the VCB threshold and activates the TIMER. The TIMER capacitor is charged by a 230A current source pull-up. At time point 6, the analog current limit loop activates. Between time point 6 and time point 7, the GATE voltage is held essentially constant and the sense voltage is regulated at VACL. As the load capacitor nears full charge, its current begins to decline. At time point 7, the load current falls and the sense voltage drops below VACL. The analog current limit loop shuts off and the GATE pin ramps further. At time point 8, the sense voltage drops below VCB and TIMER now discharges through a 5.8A current source pull-down. At time point 9, GATE reaches its maximum voltage as determined by VIN. Undervoltage Lockout Timing In Figure 9, when UV/OV drops below VUVLO (time point 1), TIMER and GATE pull low. If current has been flowing, the SENSE pin voltage decreases to zero as GATE collapses. When UV/OV recovers and clears VUVHI (time point 2), an initial time cycle begins followed by a start-up cycle. Undervoltage Timing with Overvoltage Glitch In Figure 10, when UV/OV clears VUVHI (time point 1), an initial timing cycle starts. If the system bus voltage overshoots VOVHI as shown at time point 2, TIMER discharges. At time point 3, the supply voltage recovers and drops below the VOVLO threshold. The initial timing cycle restarts followed by a start-up cycle. Overvoltage Timing During normal operation, if UV/OV exceeds VOVHI as shown at time point 1 of Figure 11, the TIMER status is unaffected. Nevertheless, GATE pulls down and disconnects the load. At time point 2, UV/OV recovers and drops below the VOVLO threshold. A gate ramp up cycle ensues.
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15
LTC4251/LTC4251-1/ LTC4251-2
APPLICATIO S I FOR ATIO
If the overvoltage glitch is long enough to deplete the load capacitor, a full start-up cycle may occur as shown between time points 3 through 6.
VIN CLEARS VLKO, CHECK VUVHI GND-VEE
UV/0V
VIN
VLKO
TIMER
5.8A VTMRL
GATE
SENSE
VOUT
425112 F07
INITIAL TIMING CYCLE
Figure 7. System Power-Up Timing (All Waveforms are Referenced to VEE)
UV/0V CLEARS VUVHI, CHECK VIN < VLKO - VLKH, TIMER < VTMRL, GATE < VGATEL AND SENSE < VCB. TIMER CLEARS VTMRL, CHECK GATE < VGATEL AND SENSE < VCB. 1 2 3 4 56 78 9
GND-VEE
UV/0V
VUVHI
VIN
VLKO VTMRH
TIMER
5.8A VTMRL 230A 5.8A 5.8A 58A 58A VACL
GATE
SENSE
VOUT
425112 F08
INITIAL TIMING CYCLE
Figure 8. Power-Up Timing with a Short-Pin (All Waveforms are Referenced to VEE)
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Timer Behavior In Figure 12a, the TIMER capacitor charges at 230A if the SENSE pin exceeds VCB. It is discharged with 5.8A if the
VTMRH 230A 5.8A 5.8A 58A 58A VACL VCB START-UP CYCLE VCB START-UP CYCLE
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LTC4251/LTC4251-1/ LTC4251-2
APPLICATIO S I FOR ATIO
SENSE pin is less than VCB. In Figure 12b, when TIMER exceeds VTMRH, TIMER is latched high by the 5.8A pullup and GATE pulls down immediately. In Figure 12c, multiple momentary faults cause the TIMER capacitor to integrate until it latches. Analog Current Limit and Fast Current Limit In Figure 13a, when SENSE exceeds VACL, GATE is regulated by the analog current limit amplifier loop. When SENSE drops below VACL, GATE is allowed to pull up. In Figure 13b, when a severe fault occurs, SENSE exceeds VFCL and GATE immediately pulls down until the analog
VUV/0V DROPS BELOW VUVLO. TIMER, GATE, AND SENSE ARE PULLED TO VEE. VUV/0V CLEARS VUVHI, CHECK TIMER < VTMRL, GATE < VGATEL AND SENSE < VCB. TIMER CLEARS VTMRL, CHECK GATE < VGATEL AND SENSE < VCB. 1 2 VUVHI VUVLO VTMRH TIMER 5.8A VTMRL 230A 5.8A 5.8A 34 56 78 9
UV/0V
GATE
SENSE
INITIAL TIMING CYCLE
Figure 9. Undervoltage Lockout Timing (All Waveforms are Referenced to VEE)
VUV/0V CLEARS VUVHI. CHECK TIMER < VTMRL, GATE < VGATEL AND SENSE < VCB. VUV/0V OVERSHOOTS VOVHI AND TIMER ABORTS INITIAL TIMING CYCLE. VUV/0V DROPS BELOW VOVLO AND TIMER RESTARTS INITIAL TIMING CYCLE. TIMER CLEARS VTMRL, CHECK GATE < VGATEL AND SENSE < VCB. 1 VOVHI UV/0V V UVHI VTMRH TIMER 5.8A VTMRL 230A 5.8A 5.8A 23 VOVLO 45 67 8 9 10
GATE
SENSE
INITIAL TIMING CYCLE
Figure 10. Undervoltage Timing with an Overvoltage Glitch (All Waveforms are Referenced to VEE)
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current amplifier can establish control. If TIMER reaches VTMRH, GATE pulls low and latches off. Resetting a Fault Latch As shown in Figure 14, a latched fault is reset by either pulling UV/OV below VUVLO or pulling TIMER below VTMRL. An initial timing cycle is initiated if UV/OV is used for reset. If TIMER is used for reset, the initial timing cycle is skipped. Internal Soft-Start An internal soft-start feature ramps the positive input of the analog current limit amplifier during initial start-up.
58A 58A VACL VCB
425112 F09
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START-UP CYCLE
58A 58A VACL VCB
425112 F10
START-UP CYCLE
17
LTC4251/LTC4251-1/ LTC4251-2
APPLICATIO S I FOR ATIO
The ramp duration is approximately 200s. This feature reduces load current dl/dt at start-up. As illustrated in Figure 15, soft-start is initiated by a TIMER transition from
VUV/0V OVERSHOOTS VOVHI AND GATE PULLS TO VEE. TIMER UNAFFECTED. VUV/0V DROPS BELOW VOVLO AND GATE RESTARTS. 1 VOVHI VOVLO VTMRH TIMER 5.8A 2 34 56 7
UV/0V
5.8A
GATE
58A VACL
SENSE
Figure 11. Overvoltage Timing (All Waveforms are Referenced to VEE)
TIMER LATCHES OFF
TIMER LATCHES OFF 1 TIMER 230A 2 5.8A 3 230A 4 5.8A VTMRH
1 TIMER 230A
2 VTMRL 5.8A 5.8A
TIMER
1 VTMRH 230A
GATE VACL SENSE VCB
GATE VACL SENSE VCB
VOUT
VOUT
CB FAULT
425112 F12a
(12a) Momentary Circuit-Breaker Fault
(12b) Circuit-Breaker Time-Out
Figure 12. Timer Behavior (All Waveforms are Referenced to VEE)
TIMER LATCHES OFF
12 TIMER 230A
34 VTMRH 5.8A 5.8A
TIMER
GATE
58A VACL
SENSE
VCB
VOUT
425112 F13a
(13a) Analog Current Limit Fault
Figure 13. Current Limit Behavior (All Waveforms are Referenced to VEE)
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VTMRH to VTMRL or when UV/OV falls below the VOVLO threshold after an OV fault. After soft-start duration, load current is limited by VACL/RS.
230A 5.8A 5.8A 58A VCB
425112 F11
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2
5.8A
GATE VACL SENSE VCB
VOUT
425112 F12c
CB FAULT
425112 F12b
(12c) Multiple Circuit-Breaker Faults
1 VTMRH 230A
2
5.8A
GATE VFCL SENSE VACL VCB
VOUT
425112 F13b
(13b) Fast Current Limit Fault
LTC4251/LTC4251-1/ LTC4251-2
APPLICATIO S I FOR ATIO
5.8A 1 2 3 TIMER V TMRL 230A 45 6 VTMRH 5.8A 5.8A
TIMER 5.8A VTMRL
RESET LATCHED TIMER FAULT BY EXTERNAL LOW PULSE.
GATE
58A 58A
GATE 58A
VACL SENSE VCB
425112 F14
Figure 14. Latched Fault Reset Timing (All Waveforms are Referenced to VEE)
PACKAGE DESCRIPTIO
(Reference LTC DWG # 05-08-1636)
0.62 MAX 0.95 REF 2.90 BSC (NOTE 4)
1.22 REF
3.85 MAX 2.62 REF
1.4 MIN
RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR
0.20 BSC 1.00 MAX DATUM `A'
0.30 - 0.50 REF 0.09 - 0.20 (NOTE 3) NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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END OF INITIAL TIMING CYCLE 1234 VTMRH 230A ~VGS(th) 5 6 VACL SENSE VCB VACL + 10mV INTERNAL SOFT-START REFERENCE 10mV
425112 F15
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Figure 15. Internal Soft-Start Timing (All Waveforms are Referenced to VEE)
S6 Package 6-Lead Plastic TSOT-23
2.80 BSC
1.50 - 1.75 (NOTE 4) PIN ONE ID
0.95 BSC
0.30 - 0.45 6 PLCS (NOTE 3)
0.80 - 0.90 0.01 - 0.10
1.90 BSC
S6 TSOT-23 0302
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LTC4251/LTC4251-1/ LTC4251-2
TYPICAL APPLICATIO S
GND GND (SHORT PIN) R1 402k 1% C1 10nF R2 32.4k 1% RIN 10k 500mW 3 VIN UV/OV 4 GATE CIN 1F R3 22 3 RC 10 CC 22nF 4 1 RS 0.01 2
425112 TA03
-48V
GND GND (SHORT PIN) R1 442k 1% C1 10nF R2 34.8k 1% RIN 10k 500mW 3 VIN UV/OV 4 GATE CIN 1F R3 31.6k CL 100F
VSUPPLY = -48V
RELATED PARTS
PART NUMBER LT1640AH/LT1640AL LT1641-1/LT1641-2 LTC1642 LTC1921 LT4250 LTC4252-1/ LTC4252-2 LTC4253 DESCRIPTION Negative High Voltage Hot Swap Controllers in SO-8 Positive High Voltage Hot Swap Controllers in SO-8 Fault Protected Hot Swap Controller Dual - 48V Supply and Fuse Monitor -48V Hot Swap Controller in SO-8 Negative Voltage Hot Swap Controller in MSOP Negative Voltage Hot Swap Controller with 3-Output Sequencer COMMENTS Negative High Voltage Supplies from -10V to -80V Supplies from 9V to 80V, Latched Off/Autoretry 3V to 16.5V, Overvoltage Protection up to 33V 1V UV and 1.5V OV Threshold Accuracy, 200V Transient Protection, Drives Three Optoisolators for Status Active Current Limiting, Supplies from -20V to -80V Fast Active Current Limiting with Drain Accelerated Response, Supplies from -15V Fast Active Current Limiting with Drain Accelerated Response, Supplies from -15V
425112fa LT 0406 REV A * PRINTED IN USA
20
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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CL 100F
+
LOAD
5
6
Q1 IRF540
LTC4251 TIMER SENSE VEE S1 CT 82nF 2 1
PUSHRESET
Figure 16. -48V/5A Application with Reverse SENSE Pin Limiting and Push-Reset at TIMER Pin
+
LOAD VOUT Q1 IRF540S 3 1 RS 0.02 2 4
425112 TA04
5
6
D1 BZX84C36 R4 22 RC 10 CC 22nF
LTC4251-1 TIMER SENSE VEE CT 220nF 2 1
Figure 17. Power-Limited Circuit Breaker Application
(c) LINEAR TECHNOLOGY CORPORATION 2001

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